Embedded high voltage (HV) transistors are gaining importance as the need for both high voltage transistors and low voltage transistors to co-exist on the same chip rises. Applications of embedded HV transistors include automobiles, displays electronics, telecommunications, and power converters. One of the common architectures used for HV devices is the lateral diffused MOS (LDMOS) transistor, such as that illustrated in FIG. 1. As shown, shallow trench isolation (STI) regions 101 are formed in an n− region 103 on p-substrate 105. Typically, n− region 103 is formed epitaxially or by well implant. Gate 107 and gate dielectric 109 are formed on a p− doped buried body 111 in n− region 103 between two STI regions 101. Source (n+) 113 and p+ region 115 are formed in buried body 111 adjacent one STI region 101, and drain (n+) 117 is formed in n− region 103 adjacent another STI region 101. An inter layer dielectric (ILD) 119 is formed over the entire device. The LDMOS transistor can operate over a wide range of breakdown voltages (from 6 volt (V) to greater than 50 V). The main challenges for HV transistors are the breakdown voltage (Vbr) and the parasitic resistance in the on-state (Rdson), which are inversely related. The n− region 103, or n− drift region, of the LDMOS is employed to increase Vbr by sustaining a larger depletion width/voltage drop. The drawback of the n− region is the higher Rdson (the sum of the resistances of the source (Rs), the channel (Rch), the drift (Rdrift), and the drain (Rd)) due to a lower doped drain.
To increase the breakdown voltage of the LDMOS, a field plate 201 or 203 has been added as illustrated in FIGS. 2A and 2B, respectively. The field plate, i.e. the extended gate 201 or extra gate 203, sits on a thicker oxide above the n− epi region 103 and could be shorted to the gate/source, floated, grounded or independently biased. The field plate helps widen the depletion width/reduce the peak electric field at the surface of the n− drift region, which in turn allows the device to sustain a larger voltage before breakdown occurs. Adverting to FIGS. 3 through 5, FIG. 3 schematically illustrates the depletion width near the gate edge for the LDMOS of FIG. 1, without a field plate. FIGS. 4 and 5 respectively show schematics of the energy band diagram extracted vertically from the field plate to the drain and the depletion width near the gate edge for the LDMOS of FIG. 2B, with a field plate. As illustrated, the depletion width increases with a field plate, the electric field is reduced, and the LDMOS has a higher Vbr. Alternatively, for a fixed blocking voltage, the n-epi concentration or the lateral extended drain (drift region) concentration may be increased, thereby reducing Rdson.
A need therefore exists for LDMOS devices exhibiting a high Vbr while maintaining a low Rsdon, and for enabling methodology.